1. Field of the Invention
This invention relates to an etching method for flattening a silicon substrate. More particularly, it is directed to etching for flattening a silicon single-crystal layer which is epitaxially grown on a silicon-crystal wafer employed as a substrate.
2. Description of the Prior Art
In the manufacture of a semiconductor integrated circuit device, there is a known process wherein a silicon single-crystal wafer to serve as a substrate is formed with a depressed portion by partial etching. A thick silicon single-crystal layer (doped with an impurity of opposite conductivity type to the substrate) is epitaxially grown on the substrate including the interior of the depressed portion. The uneven surface of the silicon layer as attributed to the depressed portion is flattened from above, and thereafter, necessary circuit elements are respectively formed in the substrate portion and the silicon layer within the depressed portion, isolation being made by a p-n junction.
In order to flatten such an uneven silicon layer, lapping, or the like, mechanical polishing has hitherto been mainly adoapted. The mechanical polishing method, however, involves such disadvantages (1) that after the polishing, crystal defects appear in the flattened silicon surface, (2) that the polishing period of time is considerably long, which incurs an increase in cost, and (3) that the control of the position (thickness) of the final finished surface is difficult. In general, where an epitaxial silicon layer is to be isolated by a p-n junction, especially where the epitaxial layer is thick, the diffusion depth for the isolation is great, so that a long time is required for the formation of an isolation layer. Further, as a consequence of the long time, the diffused isolation layer spreads widely in the lateral direction, and the density of integration is lowered to that extent.